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MC14049B, MC14050B Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting Hex Buffer are constructed with MOS P-Channel and N-Channel enhancement mode devices in a single monolithic structure. These complementary MOS devices find primary use where low power dissipation and/or high noise immunity is desired. These devices provide logic level conversion using only one supply voltage, VDD. The input-signal high level (VIH) can exceed the VDD supply voltage for logic level conversions. Two TTL/DTL loads can be driven when the devices are used as a CMOS-to-TTL/DTL converter (VDD = 5.0 V, VOL 0.4 V, IOL 3.2 mA). Note that pins 13 and 16 are not connected internally on these devices; consequently connections to these terminals will not affect circuit operation.
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16 PDIP-16 P SUFFIX CASE 648 MC140XXBCP AWLYYWW 1 16 SOIC-16 D SUFFIX CASE 751B 140XXB AWLYWW 1 16 TSSOP-16 DT SUFFIX CASE 948F 16 1 MC140XXB AWLYWW 14 0XXB ALYW
v
* * * * * *
High Source and Sink Currents High-to-Low Level Converter Supply Voltage Range = 3.0 V to 18 V VIN can exceed VDD Meets JEDEC B Specifications Improved ESD Protection On All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol VDD Vin Vout Iin Iout PD Parameter DC Supply Voltage Range Input Voltage Range (DC or Transient) Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) (Plastic) (SOIC) Ambient Temperature Range Storage Temperature Range Lead Temperature (8-Second Soldering) Value - 0.5 to +18.0 - 0.5 to +18.0 - 0.5 to VDD + 0.5 10 45 Unit V V V mA mA mW MC14049BCP 825 740 - 55 to +125 - 65 to +150 260 C C C MC14049BD MC14049BDR2 MC14049BF MC14050BCP MC14050BD MC14050BDR2 MC14050BDTEL MC14050BF MC14050BFEL PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 PDIP-16 SOIC-16 SOIC-16 SOEIAJ-16 F SUFFIX CASE 966
1 XX = Specific Device Code A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week
ORDERING INFORMATION
Device Package Shipping 2000/Box 2400/Box 2500/Tape & Reel See Note 1. 2000/Box 2400/Box 2500/Tape & Reel
TA Tstg TL
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: See Figure 3. This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields referenced to the VSS pin only. Extra precautions must be taken to avoid applications of any voltage higher than the maximum rated voltages to this high-impedance circuit. For proper operation, the ranges VSS Vin 18 V and VSS Vout VDD are recommended. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
TSSOP-16 2000/Tape & Reel SOEIAJ-16 SOEIAJ-16 See Note 1. See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
(c) Semiconductor Components Industries, LLC, 2000
1
March, 2000 - Rev. 3
Publication Order Number: MC14049B/D
MC14049B, MC14050B
PIN ASSIGNMENT
VDD OUTA INA OUTB INB OUTC INC VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC OUTF INF NC OUTE INE OUTD IND
MC14049B 3 5 7 9 11 14 NC = PIN 13, 16 VSS = PIN 8 VDD = PIN 1 2 4 6 10 12 15
LOGIC DIAGRAM
3 5 7 9 11 14
MC14050B 2 4 6 10 12 15 NC = PIN 13, 16 VSS = PIN 8 VDD = PIN 1
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I II I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIII II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I III II IIII I III I III I I IIIIIIIIIIII IIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I I I I III II IIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II II IIII I I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II IIII I III II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I I I I I I II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III III I I I I I I I I I III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIIIIIIIIIII I II IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III II I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at + 25_C 6. To calculate total supply current at loads other than 50 pF:
Where: IT is in A (per Package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency and k = 0.002.
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Total Supply Current (5.) (6.) (Dynamic plus Quiescent, per package) (CL = 50 pF on all outputs, all buffers switching
Quiescent Current (Per Package)
Input Capacitance (Vin = 0)
Input Current
Output Drive Current (VOH = 2.5 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)
Input Voltage (VO = 4.5 Vdc) (VO = 9.0 Vdc) (VO = 13.5 Vdc)
Output Voltage Vin = VDD
(VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)
(VO = 0.5 Vdc) (VO = 1.0 Vdc) (VO = 1.5 Vdc)
Vin = 0
Characteristic
IT(CL) = IT(50 pF) + (CL - 50) Vfk
"0" Level
"1" Level
"1" Level
"0" Level
Source
Sink
Symbol
VOH
VOL
IOH
VIH
IDD
Cin
IOL
VIL
Iin
IT
VDD Vdc
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
15
--
MC14049B, MC14050B
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4.95 9.95 14.95 - 1.6 - 1.6 - 4.7 3.75 10 30 MinIII Max 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- - 55_C 0.1 0.05 0.05 0.05 1.0 2.0 4.0 1.5 3.0 4.0 --IIII 10 -- -- -- -- -- -- -- -- -- -- -- -- -- - 1.25 - 1.30 - 3.75 4.95 9.95 14.95 Min 3.2 8.0 24 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- IT = (1.8 A/kHz) f + IDD IT = (3.5 A/kHz) f + IDD IT = (5.3 A/kHz) f + IDD 0.00001 Typ (4.) + 25_C 0.002 0.004 0.006 - 2.5 - 2.6 - 10 2.75 5.50 8.25 2.25 4.50 6.75 6.0 16 40 5.0 10 15 0 0 0 0.1 0.05 0.05 0.05 Max 1.0 2.0 4.0 1.5 3.0 4.0 20 -- -- -- -- -- -- -- -- -- -- -- 4.95 9.95 14.95 - 1.0 - 1.0 - 3.0 Min 2.6 6.6 19 3.5 7.0 11 -- -- -- -- -- -- -- -- -- -- -- + 125_C 1.0 0.05 0.05 0.05 Max 30 60 120 1.5 3.0 4.0 -- -- -- -- -- -- -- -- -- -- -- -- -- mAdc mAdc Adc Adc Adc Unit Vdc Vdc Vdc Vdc pF
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MC14049B, MC14050B
I OH , OUTPUT SOURCE CURRNT (mAdc)
VGS = 5.0 Vdc - 10
- 20 VGS = 10 Vdc
I OL, OUTPUT SINK CURRENT (mAdc)
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I IIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I III I I I I I IIIII I IIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII I IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
AC SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = + 25_C)
Characteristic Symbol tTLH VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 5.0 10 15 Min -- -- -- -- -- -- -- -- -- -- -- -- Typ (8.) 100 50 40 40 20 15 80 40 30 40 20 15 Max 160 80 60 60 40 30 Unit ns Output Rise Time tTLH = (0.7 ns/pF) CL + 65 ns tTLH = (0.25 ns/pF) CL + 37.5 ns tTLH = (0.2 ns/pF) CL + 30 ns Output Fall Time tTHL = (0.2 ns/pF) CL + 30 ns tTHL = (0.06 ns/pF) CL + 17 ns tTHL = (0.04 ns/pF) CL + 13 ns tTHL ns Propagation Delay Time tPLH = (0.33 ns/pF) CL + 63.5 ns tPLH = (0.19 ns/pF) CL + 30.5 ns tPLH = (0.06 ns/pF) CL + 27 ns Propagation Delay Time tPHL = (0.2 ns/pF) CL + 30 ns tPHL = (0.1 ns/pF) CL + 15 ns tPHL = (0.05 ns/pF) CL + 12.5 ns tPLH ns 140 80 60 80 40 30 tPHL ns 7. The formulas given are for the typical characteristics only at 25_C. 8. Data labeled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. MC14049B VDD 1 IOH 8 VSS VDS = VOH - VDD VOH 8 VSS MC14050B VDD 1 IOL VOL 8 VSS VDD = VOL MC14049B VDD 1 IOL VOL 8 VSS MC14050B VDD 1 IOH VOH 0 160 VGS = 15 Vdc 120 80 VGS = 10 Vdc - 30 MAXIMUM CURRENT LEVEL 40 VGS = 5.0 Vdc 0 0 2.0 4.0 6.0 8.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) 10 - 40 VGS = 15 Vdc MAXIMUM CURRENT LEVEL 0 - 50 - 10 - 8.0 - 6.0 - 4.0 - 2.0 VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 1. Typical Output Source Characteristics
Figure 2. Typical Output Sink Characteristics
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MC14049B, MC14050B
PD , MAXIMUM POWER DISSIPATION (mW) PER PACKAGE 1200 1100 1000 900 825 800 740 700 600 500 400 300 200 100 0 25 (D) SOIC 175 mW (P) 120 mW (D) 50 75 100 125 TA, AMBIENT TEMPERATURE (C) 150 175 (P) PDIP
Figure 3. Ambient Temperature Power Derating
20 ns INPUT VDD 1 # PULSE GENERATOR OUTPUT MC14049B Vin 8 VSS CL Vout tPLH tPHL OUTPUT MC14050B 90% 50% 10% tTLH tPHL 90% 50% 10% tTHL 90% 50% 10%
20 ns VDD
VSS tPLH VOH
tTLH tPHL
VOL
VOH
# Invert on MC14049B only
VOL tTHL
Figure 4. Switching Time Test Circuit and Waveforms
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MC14049B, MC14050B
PACKAGE DIMENSIONS
-A-
16 9
PDIP-16 P SUFFIX PLASTIC DIP PACKAGE CASE 648-08 ISSUE R
B
1
8
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01
F S
C
L
-T- H G D
16 PL
SEATING PLANE
K
J TA
M
M
0.25 (0.010)
M
-A-
SOIC-16 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
16
9
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
DIM A B C D F G J K M P R
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MC14049B, MC14050B
PACKAGE DIMENSIONS
TSSOP-16 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O
16X K REF
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
K K1
16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
2X
L/2
J1 B -U-
L
PIN 1 IDENT. 1 8
SECTION N-N J
N 0.25 (0.010) 0.15 (0.006) T U
S
A -V- N F DETAIL E
C 0.10 (0.004) -T- SEATING
PLANE
H D G
DETAIL E
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EEE CCC EEE CCC
M
9
-W-
MC14049B, MC14050B
PACKAGE DIMENSIONS
SOEIAJ-16 F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 966-01 ISSUE O
LE Q1 E HE
1 8
16
9
M_ L DETAIL P
Z D e A VIEW P
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.78 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.031
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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PUBLICATION ORDERING INFORMATION
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MC14049B/D

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